/****************************************************************************
 *
 * Copyright 2017 Samsung Electronics All Rights Reserved.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing,
 * software distributed under the License is distributed on an
 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
 * either express or implied. See the License for the specific
 * language governing permissions and limitations under the License.
 *
 ****************************************************************************/
/****************************************************************************
 * arch/arm/src/s5j/chip/s5j200_pwm.h
 *
 *   Copyright (C) 2009-2010, 2014-2015 Gregory Nutt. All rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name NuttX nor the names of its contributors may be
 *    used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 ****************************************************************************/

#ifndef __ARCH_ARM_SRC_S5J_CHIP_S5JT200_PWM_H
#define __ARCH_ARM_SRC_S5J_CHIP_S5JT200_PWM_H

/****************************************************************************
 * Include
 ****************************************************************************/
#include "s5j_memorymap.h"

/****************************************************************************
 * Pre-processor Definitions
 ****************************************************************************/
/* PWM Register Offsets *****************************************************/
#define S5J_PWM_TCFG0_OFFSET		0x00
#define S5J_PWM_TCFG1_OFFSET		0x04
#define S5J_PWM_TCON_OFFSET			0x08
#define S5J_PWM_TCNTB0_OFFSET		0x0C
#define S5J_PWM_TCMPB0_OFFSET		0x10
#define S5J_PWM_TCNTO0_OFFSET		0x14
#define S5J_PWM_TCNTB1_OFFSET		0x1C
#define S5J_PWM_TCMPB1_OFFSET		0x20
#define S5J_PWM_TCNTO1_OFFSET		0x24
#define S5J_PWM_TCNTB2_OFFSET		0x1C
#define S5J_PWM_TCMPB2_OFFSET		0x20
#define S5J_PWM_TCNTO2_OFFSET		0x24
#define S5J_PWM_TCNTB3_OFFSET		0x2C
#define S5J_PWM_TCMPB3_OFFSET		0x30
#define S5J_PWM_TCNTO3_OFFSET		0x34
#define S5J_PWM_TINT_CSTAT_OFFSET	0x44

#define S5J_PWM_TCNTB_OFFSET(c)		(S5J_PWM_TCNTB0_OFFSET + 0xc * (c))
#define S5J_PWM_TCMPB_OFFSET(c)		(S5J_PWM_TCMPB0_OFFSET + 0xc * (c))
#define S5J_PWM_TCNTO_OFFSET(c)		(S5J_PWM_TCNTO0_OFFSET + 0xc * (c))

/* PWM0 Register Address ****************************************************/
#define S5J_PWM0_TCFG0			(S5J_PWM0_BASE + S5J_PWM_TCFG0_OFFSET)
#define S5J_PWM0_TCFG1			(S5J_PWM0_BASE + S5J_PWM_TCFG1_OFFSET)
#define S5J_PWM0_TCON			(S5J_PWM0_BASE + S5J_PWM_TCON_OFFSET)
#define S5J_PWM0_TCNTB0			(S5J_PWM0_BASE + S5J_PWM_TCNTB0_OFFSET)
#define S5J_PWM0_TCMPB0			(S5J_PWM0_BASE + S5J_PWM_TCMPB0_OFFSET)
#define S5J_PWM0_TCNTO0			(S5J_PWM0_BASE + S5J_PWM_TCNTO0_OFFSET)
#define S5J_PWM0_TCNTB1			(S5J_PWM0_BASE + S5J_PWM_TCNTB1_OFFSET)
#define S5J_PWM0_TCMPB1			(S5J_PWM0_BASE + S5J_PWM_TCMPB1_OFFSET)
#define S5J_PWM0_TCNTO1			(S5J_PWM0_BASE + S5J_PWM_TCNTO1_OFFSET)
#define S5J_PWM0_TCNTB2			(S5J_PWM0_BASE + S5J_PWM_TCNTB2_OFFSET)
#define S5J_PWM0_TCMPB2			(S5J_PWM0_BASE + S5J_PWM_TCMPB2_OFFSET)
#define S5J_PWM0_TCNTO2			(S5J_PWM0_BASE + S5J_PWM_TCNTO2_OFFSET)
#define S5J_PWM0_TCNTB3			(S5J_PWM0_BASE + S5J_PWM_TCNTB3_OFFSET)
#define S5J_PWM0_TCMPB3			(S5J_PWM0_BASE + S5J_PWM_TCMPB3_OFFSET)
#define S5J_PWM0_TCNTO3			(S5J_PWM0_BASE + S5J_PWM_TCNTO3_OFFSET)
#define S5J_PWM0_TINT_CSTAT		(S5J_PWM0_BASE + S5J_PWM_TINT_CSTAT_OFFSET)

/* PWM1 Register Address ****************************************************/
#define S5J_PWM1_TCFG0			(S5J_PWM1_BASE + S5J_PWM_TCFG0_OFFSET)
#define S5J_PWM1_TCFG1			(S5J_PWM1_BASE + S5J_PWM_TCFG1_OFFSET)
#define S5J_PWM1_TCON			(S5J_PWM1_BASE + S5J_PWM_TCON_OFFSET)
#define S5J_PWM1_TCNTB0			(S5J_PWM1_BASE + S5J_PWM_TCNTB0_OFFSET)
#define S5J_PWM1_TCMPB0			(S5J_PWM1_BASE + S5J_PWM_TCMPB0_OFFSET)
#define S5J_PWM1_TCNTO0			(S5J_PWM1_BASE + S5J_PWM_TCNTO0_OFFSET)
#define S5J_PWM1_TCNTB1			(S5J_PWM1_BASE + S5J_PWM_TCNTB1_OFFSET)
#define S5J_PWM1_TCMPB1			(S5J_PWM1_BASE + S5J_PWM_TCMPB1_OFFSET)
#define S5J_PWM1_TCNTO1			(S5J_PWM1_BASE + S5J_PWM_TCNTO1_OFFSET)
#define S5J_PWM1_TCNTB2			(S5J_PWM1_BASE + S5J_PWM_TCNTB2_OFFSET)
#define S5J_PWM1_TCMPB2			(S5J_PWM1_BASE + S5J_PWM_TCMPB2_OFFSET)
#define S5J_PWM1_TCNTO2			(S5J_PWM1_BASE + S5J_PWM_TCNTO2_OFFSET)
#define S5J_PWM1_TCNTB3			(S5J_PWM1_BASE + S5J_PWM_TCNTB3_OFFSET)
#define S5J_PWM1_TCMPB3			(S5J_PWM1_BASE + S5J_PWM_TCMPB3_OFFSET)
#define S5J_PWM1_TCNTO3			(S5J_PWM1_BASE + S5J_PWM_TCNTO3_OFFSET)
#define S5J_PWM1_TINT_CSTAT		(S5J_PWM1_BASE + S5J_PWM_TINT_CSTAT_OFFSET)

/* Register Bitfield Definitions ********************************************/
/* TCFG0 ********************************************************************/
#define PWM_TCFG0_DEADZONE_LENGTH_SHIFT	16
#define PWM_TCFG0_DEADZONE_LENGTH_MASK	(0xff << PWM_TCFG0_DEADZONE_LENGTH_SHIFT)

#define PWM_TCFG0_PRESCALER0_SHIFT		0
#define PWM_TCFG0_PRESCALER0_MASK		(0xff << PWM_TCFG0_PRESCALER0_SHIFT)
#define PWM_TCFG0_PRESCALER0_RESET		(0x01 << PWM_TCFG0_PRESCALER0_SHIFT)

#define PWM_TCFG0_PRESCALER1_SHIFT		8
#define PWM_TCFG0_PRESCALER1_MASK		(0xff << PWM_TCFG0_PRESCALER1_SHIFT)
#define PWM_TCFG0_PRESCALER1_RESET		(0x01 << PWM_TCFG0_PRESCALER1_SHIFT)

/* TCFG1 ********************************************************************/
#define PWM_TCFG1_DIVIDER_MUX_SHIFT(c)	(4 * c)
#define PWM_TCFG1_DIVIDER_MUX_MASK(c)	(0x7 << PWM_TCFG1_DIVIDER_MUX_SHIFT(c))
#define PWM_TCFG1_DIVIDER_MUX_DIV1(c)	(0x0 << PWM_TCFG1_DIVIDER_MUX_SHIFT(c))
#define PWM_TCFG1_DIVIDER_MUX_DIV2(c)	(0x1 << PWM_TCFG1_DIVIDER_MUX_SHIFT(c))
#define PWM_TCFG1_DIVIDER_MUX_DIV4(c)	(0x2 << PWM_TCFG1_DIVIDER_MUX_SHIFT(c))
#define PWM_TCFG1_DIVIDER_MUX_DIV8(c)	(0x3 << PWM_TCFG1_DIVIDER_MUX_SHIFT(c))
#define PWM_TCFG1_DIVIDER_MUX_DIV16(c)	(0x4 << PWM_TCFG1_DIVIDER_MUX_SHIFT(c))

#define PWM_TCFG1_DIVIDER_MUX3_SHIFT	PWM_TCFG1_DIVIDER_MUX_SHIFT(3)
#define PWM_TCFG1_DIVIDER_MUX3_MASK		PWM_TCFG1_DIVIDER_MUX_MASK(3)
#define PWM_TCFG1_DIVIDER_MUX3_DIV1		PWM_TCFG1_DIVIDER_MUX_DIV1(3)
#define PWM_TCFG1_DIVIDER_MUX3_DIV2		PWM_TCFG1_DIVIDER_MUX_DIV2(3)
#define PWM_TCFG1_DIVIDER_MUX3_DIV4		PWM_TCFG1_DIVIDER_MUX_DIV4(3)
#define PWM_TCFG1_DIVIDER_MUX3_DIV8		PWM_TCFG1_DIVIDER_MUX_DIV8(3)
#define PWM_TCFG1_DIVIDER_MUX3_DIV16	PWM_TCFG1_DIVIDER_MUX_DIV16(3)

#define PWM_TCFG1_DIVIDER_MUX2_SHIFT	PWM_TCFG1_DIVIDER_MUX_SHIFT(2)
#define PWM_TCFG1_DIVIDER_MUX2_MASK		PWM_TCFG1_DIVIDER_MUX_MASK(2)
#define PWM_TCFG1_DIVIDER_MUX2_DIV1		PWM_TCFG1_DIVIDER_MUX_DIV1(2)
#define PWM_TCFG1_DIVIDER_MUX2_DIV2		PWM_TCFG1_DIVIDER_MUX_DIV2(2)
#define PWM_TCFG1_DIVIDER_MUX2_DIV4		PWM_TCFG1_DIVIDER_MUX_DIV4(2)
#define PWM_TCFG1_DIVIDER_MUX2_DIV8		PWM_TCFG1_DIVIDER_MUX_DIV8(2)
#define PWM_TCFG1_DIVIDER_MUX2_DIV16	PWM_TCFG1_DIVIDER_MUX_DIV16(2)

#define PWM_TCFG1_DIVIDER_MUX1_SHIFT	PWM_TCFG1_DIVIDER_MUX_SHIFT(1)
#define PWM_TCFG1_DIVIDER_MUX1_MASK		PWM_TCFG1_DIVIDER_MUX_MASK(1)
#define PWM_TCFG1_DIVIDER_MUX1_DIV1		PWM_TCFG1_DIVIDER_MUX_DIV1(1)
#define PWM_TCFG1_DIVIDER_MUX1_DIV2		PWM_TCFG1_DIVIDER_MUX_DIV2(1)
#define PWM_TCFG1_DIVIDER_MUX1_DIV4		PWM_TCFG1_DIVIDER_MUX_DIV4(1)
#define PWM_TCFG1_DIVIDER_MUX1_DIV8		PWM_TCFG1_DIVIDER_MUX_DIV8(1)
#define PWM_TCFG1_DIVIDER_MUX1_DIV16	PWM_TCFG1_DIVIDER_MUX_DIV16(1)

#define PWM_TCFG1_DIVIDER_MUX0_SHIFT	PWM_TCFG1_DIVIDER_MUX_SHIFT(0)
#define PWM_TCFG1_DIVIDER_MUX0_MASK		PWM_TCFG1_DIVIDER_MUX_MASK(0)
#define PWM_TCFG1_DIVIDER_MUX0_DIV1		PWM_TCFG1_DIVIDER_MUX_DIV1(0)
#define PWM_TCFG1_DIVIDER_MUX0_DIV2		PWM_TCFG1_DIVIDER_MUX_DIV2(0)
#define PWM_TCFG1_DIVIDER_MUX0_DIV4		PWM_TCFG1_DIVIDER_MUX_DIV4(0)
#define PWM_TCFG1_DIVIDER_MUX0_DIV8		PWM_TCFG1_DIVIDER_MUX_DIV8(0)
#define PWM_TCFG1_DIVIDER_MUX0_DIV16	PWM_TCFG1_DIVIDER_MUX_DIV16(0)

/* TCON *********************************************************************/
#define PWM_TCON_TIM_BIT_OFFSET(c)			(((c) == 0 ? 0 : ((c) + 1)) * 4)

#define PWM_TCON_TIM_STARTSTOP_SHIFT(c)		PWM_TCON_TIM_BIT_OFFSET(c)
#define PWM_TCON_TIM_STARTSTOP_MASK(c)		(0x1 << PWM_TCON_TIM_STARTSTOP_SHIFT(c))
#define PWM_TCON_TIM_STARTSTOP_STOP(c)		(0x0 << PWM_TCON_TIM_STARTSTOP_SHIFT(c))
#define PWM_TCON_TIM_STARTSTOP_START(c)		(0x1 << PWM_TCON_TIM_STARTSTOP_SHIFT(c))

#define PWM_TCON_TIM_MAN_UPDATE_SHIFT(c)	(PWM_TCON_TIM_BIT_OFFSET(c) + 1)
#define PWM_TCON_TIM_MAN_UPDATE_MASK(c)		(0x1 << PWM_TCON_TIM_MAN_UPDATE_SHIFT(c))
#define PWM_TCON_TIM_MAN_UPDATE_NOP(c)		(0x0 << PWM_TCON_TIM_MAN_UPDATE_SHIFT(c))
#define PWM_TCON_TIM_MAN_UPDATE_UPDATE(c)	(0x1 << PWM_TCON_TIM_MAN_UPDATE_SHIFT(c))

#define PWM_TCON_TIM_OUTPUT_INV_SHIFT(c)	(PWM_TCON_TIM_BIT_OFFSET(c) + 2)
#define PWM_TCON_TIM_OUTPUT_INV_MASK(c)		(0x1 << PWM_TCON_TIM_OUTPUT_INV_SHIFT(c))
#define PWM_TCON_TIM_OUTPUT_INV_OFF(c)		(0x0 << PWM_TCON_TIM_OUTPUT_INV_SHIFT(c))
#define PWM_TCON_TIM_OUTPUT_INV_ON(c)		(0x1 << PWM_TCON_TIM_OUTPUT_INV_SHIFT(c))

#define PWM_TCON_TIM_AUTO_RELOAD_SHIFT(c)	(PWM_TCON_TIM_BIT_OFFSET(c) + 3)
#define PWM_TCON_TIM_AUTO_RELOAD_MASK(c)	(0x1 << PWM_TCON_TIM_AUTO_RELOAD_SHIFT(c))
#define PWM_TCON_TIM_AUTO_RELOAD_OFF(c)		(0x0 << PWM_TCON_TIM_AUTO_RELOAD_SHIFT(c))
#define PWM_TCON_TIM_AUTO_RELOAD_ON(c)		(0x1 << PWM_TCON_TIM_AUTO_RELOAD_SHIFT(c))

#define PWM_TCON_TIM0_STARTSTOP_SHIFT		PWM_TCON_TIM_BIT_OFFSET(0)
#define PWM_TCON_TIM0_STARTSTOP_MASK		(0x1 << PWM_TCON_TIM_STARTSTOP_SHIFT(0))
#define PWM_TCON_TIM0_STARTSTOP_STOP		(0x0 << PWM_TCON_TIM_STARTSTOP_SHIFT(0))
#define PWM_TCON_TIM0_STARTSTOP_START		(0x1 << PWM_TCON_TIM_STARTSTOP_SHIFT(0))

#define PWM_TCON_TIM0_MAN_UPDATE_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(0) + 1)
#define PWM_TCON_TIM0_MAN_UPDATE_MASK		(0x1 << PWM_TCON_TIM_MAN_UPDATE_SHIFT(0))
#define PWM_TCON_TIM0_MAN_UPDATE_NOP		(0x0 << PWM_TCON_TIM_MAN_UPDATE_SHIFT(0))
#define PWM_TCON_TIM0_MAN_UPDATE_UPDATE		(0x1 << PWM_TCON_TIM_MAN_UPDATE_SHIFT(0))

#define PWM_TCON_TIM0_OUTPUT_INV_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(0) + 2)
#define PWM_TCON_TIM0_OUTPUT_INV_MASK		(0x1 << PWM_TCON_TIM_OUTPUT_INV_SHIFT(0))
#define PWM_TCON_TIM0_OUTPUT_INV_OFF		(0x0 << PWM_TCON_TIM_OUTPUT_INV_SHIFT(0))
#define PWM_TCON_TIM0_OUTPUT_INV_ON			(0x1 << PWM_TCON_TIM_OUTPUT_INV_SHIFT(0))

#define PWM_TCON_TIM0_AUTO_RELOAD_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(0) + 3)
#define PWM_TCON_TIM0_AUTO_RELOAD_MASK		(0x1 << PWM_TCON_TIM_AUTO_RELOAD_SHIFT(0))
#define PWM_TCON_TIM0_AUTO_RELOAD_OFF		(0x0 << PWM_TCON_TIM_AUTO_RELOAD_SHIFT(0))
#define PWM_TCON_TIM0_AUTO_RELOAD_ON		(0x1 << PWM_TCON_TIM_AUTO_RELOAD_SHIFT(0))

#define PWM_TCON_TIM0_DEADZONE_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(0) + 4)
#define PWM_TCON_TIM0_DEADZONE_MASK			(0x1 << PWM_TCON_TIM0_DEADZONE_SHIFT)
#define PWM_TCON_TIM0_DEADZONE_DISABLE		(0x0 << PWM_TCON_TIM0_DEADZONE_SHIFT)
#define PWM_TCON_TIM0_DEADZONE_ENABLE		(0x1 << PWM_TCON_TIM0_DEADZONE_SHIFT)

#define PWM_TCON_TIM1_STARTSTOP_SHIFT		PWM_TCON_TIM_BIT_OFFSET(1)
#define PWM_TCON_TIM1_STARTSTOP_MASK		(0x1 << PWM_TCON_TIM1_STARTSTOP_SHIFT)
#define PWM_TCON_TIM1_STARTSTOP_STOP		(0x0 << PWM_TCON_TIM1_STARTSTOP_SHIFT)
#define PWM_TCON_TIM1_STARTSTOP_START		(0x1 << PWM_TCON_TIM1_STARTSTOP_SHIFT)

#define PWM_TCON_TIM1_MAN_UPDATE_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(1) + 1)
#define PWM_TCON_TIM1_MAN_UPDATE_MASK		(0x1 << PWM_TCON_TIM1_MAN_UPDATE_SHIFT)
#define PWM_TCON_TIM1_MAN_UPDATE_NOP		(0x0 << PWM_TCON_TIM1_MAN_UPDATE_SHIFT)
#define PWM_TCON_TIM1_MAN_UPDATE_UPDATE		(0x1 << PWM_TCON_TIM1_MAN_UPDATE_SHIFT)

#define PWM_TCON_TIM1_OUTPUT_INV_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(1) + 2)
#define PWM_TCON_TIM1_OUTPUT_INV_MASK		(0x1 << PWM_TCON_TIM1_OUTPUT_INV_SHIFT)
#define PWM_TCON_TIM1_OUTPUT_INV_OFF		(0x0 << PWM_TCON_TIM1_OUTPUT_INV_SHIFT)
#define PWM_TCON_TIM1_OUTPUT_INV_ON			(0x1 << PWM_TCON_TIM1_OUTPUT_INV_SHIFT)

#define PWM_TCON_TIM1_AUTO_RELOAD_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(1) + 3)
#define PWM_TCON_TIM1_AUTO_RELOAD_MASK		(0x1 << PWM_TCON_TIM1_AUTO_RELOAD_SHIFT)
#define PWM_TCON_TIM1_AUTO_RELOAD_OFF		(0x0 << PWM_TCON_TIM1_AUTO_RELOAD_SHIFT)
#define PWM_TCON_TIM1_AUTO_RELOAD_ON		(0x1 << PWM_TCON_TIM1_AUTO_RELOAD_SHIFT)

#define PWM_TCON_TIM2_STARTSTOP_SHIFT		PWM_TCON_TIM_BIT_OFFSET(2)
#define PWM_TCON_TIM2_STARTSTOP_MASK		(0x1 << PWM_TCON_TIM2_STARTSTOP_SHIFT)
#define PWM_TCON_TIM2_STARTSTOP_STOP		(0x0 << PWM_TCON_TIM2_STARTSTOP_SHIFT)
#define PWM_TCON_TIM2_STARTSTOP_START		(0x1 << PWM_TCON_TIM2_STARTSTOP_SHIFT)

#define PWM_TCON_TIM2_MAN_UPDATE_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(2) + 1)
#define PWM_TCON_TIM2_MAN_UPDATE_MASK		(0x1 << PWM_TCON_TIM2_MAN_UPDATE_SHIFT)
#define PWM_TCON_TIM2_MAN_UPDATE_NOP		(0x0 << PWM_TCON_TIM2_MAN_UPDATE_SHIFT)
#define PWM_TCON_TIM2_MAN_UPDATE_UPDATE		(0x1 << PWM_TCON_TIM2_MAN_UPDATE_SHIFT)

#define PWM_TCON_TIM2_OUTPUT_INV_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(2) + 2)
#define PWM_TCON_TIM2_OUTPUT_INV_MASK		(0x1 << PWM_TCON_TIM2_OUTPUT_INV_SHIFT)
#define PWM_TCON_TIM2_OUTPUT_INV_OFF		(0x0 << PWM_TCON_TIM2_OUTPUT_INV_SHIFT)
#define PWM_TCON_TIM2_OUTPUT_INV_ON			(0x1 << PWM_TCON_TIM2_OUTPUT_INV_SHIFT)

#define PWM_TCON_TIM2_AUTO_RELOAD_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(2) + 3)
#define PWM_TCON_TIM2_AUTO_RELOAD_MASK		(0x1 << PWM_TCON_TIM2_AUTO_RELOAD_SHIFT)
#define PWM_TCON_TIM2_AUTO_RELOAD_OFF		(0x0 << PWM_TCON_TIM2_AUTO_RELOAD_SHIFT)
#define PWM_TCON_TIM2_AUTO_RELOAD_ON		(0x1 << PWM_TCON_TIM2_AUTO_RELOAD_SHIFT)

#define PWM_TCON_TIM3_STARTSTOP_SHIFT		PWM_TCON_TIM_BIT_OFFSET(3)
#define PWM_TCON_TIM3_STARTSTOP_MASK		(0x1 << PWM_TCON_TIM3_STARTSTOP_SHIFT)
#define PWM_TCON_TIM3_STARTSTOP_STOP		(0x0 << PWM_TCON_TIM3_STARTSTOP_SHIFT)
#define PWM_TCON_TIM3_STARTSTOP_START		(0x1 << PWM_TCON_TIM3_STARTSTOP_SHIFT)

#define PWM_TCON_TIM3_MAN_UPDATE_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(3) + 1)
#define PWM_TCON_TIM3_MAN_UPDATE_MASK		(0x1 << PWM_TCON_TIM3_MAN_UPDATE_SHIFT)
#define PWM_TCON_TIM3_MAN_UPDATE_NOP		(0x0 << PWM_TCON_TIM3_MAN_UPDATE_SHIFT)
#define PWM_TCON_TIM3_MAN_UPDATE_UPDATE		(0x1 << PWM_TCON_TIM3_MAN_UPDATE_SHIFT)

#define PWM_TCON_TIM3_OUTPUT_INV_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(3) + 2)
#define PWM_TCON_TIM3_OUTPUT_INV_MASK		(0x1 << PWM_TCON_TIM3_OUTPUT_INV_SHIFT)
#define PWM_TCON_TIM3_OUTPUT_INV_OFF		(0x0 << PWM_TCON_TIM3_OUTPUT_INV_SHIFT)
#define PWM_TCON_TIM3_OUTPUT_INV_ON			(0x1 << PWM_TCON_TIM3_OUTPUT_INV_SHIFT)

#define PWM_TCON_TIM3_AUTO_RELOAD_SHIFT		(PWM_TCON_TIM_BIT_OFFSET(3) + 3)
#define PWM_TCON_TIM3_AUTO_RELOAD_MASK		(0x1 << PWM_TCON_TIM3_AUTO_RELOAD_SHIFT)
#define PWM_TCON_TIM3_AUTO_RELOAD_OFF		(0x0 << PWM_TCON_TIM3_AUTO_RELOAD_SHIFT)
#define PWM_TCON_TIM3_AUTO_RELOAD_ON		(0x1 << PWM_TCON_TIM3_AUTO_RELOAD_SHIFT)

/* TINT_CSTAT ***************************************************************/
#define PWM_TINT_CSTAT_TIM0_INTMASK_SHIFT	0
#define PWM_TINT_CSTAT_TIM0_INTMASK_MASK	(0x1 << PWM_TINT_CSTAT_TIM0_INTMASk_SHIFT)

#define PWM_TINT_CSTAT_TIM1_INTMASK_SHIFT	1
#define PWM_TINT_CSTAT_TIM1_INTMASK_MASK	(0x1 << PWM_TINT_CSTAT_TIM1_INTMASK_SHIFT)

#define PWM_TINT_CSTAT_TIM2_INTMASK_SHIFT	2
#define PWM_TINT_CSTAT_TIM2_INTMASK_MASK	(0x1 << PWM_TINT_CSTAT_TIM2_INTMASK_SHIFT)

#define PWM_TINT_CSTAT_TIM3_INTMASK_SHIFT	3
#define PWM_TINT_CSTAT_TIM3_INTMASK_MASK	(0x1 << PWM_TINT_CSTAT_TIM3_INTMASK_SHIFT)

#define PWM_TINT_CSTAT_TIM0_INTPND_SHIFT	5
#define PWM_TINT_CSTAT_TIM0_INTPND_MASK		(0x1 << PWM_TINT_CSTAT_TIM0_INTPND_SHIFT)

#define PWM_TINT_CSTAT_TIM1_INTPND_SHIFT	6
#define PWM_TINT_CSTAT_TIM1_INTPND_MASK		(0x1 << PWM_TINT_CSTAT_TIM1_INTPND_SHIFT)

#define PWM_TINT_CSTAT_TIM2_INTPND_SHIFT	7
#define PWM_TINT_CSTAT_TIM2_INTPND_MASK		(0x1 << PWM_TINT_CSTAT_TIM2_INTPND_SHIFT)

#define PWM_TINT_CSTAT_TIM3_INTPND_SHIFT	8
#define PWM_TINT_CSTAT_TIM3_INTPND_MASK		(0x1 << PWM_TINT_CSTAT_TIM3_INTPND_SHIFT)

#endif /* __ARCH_ARM_SRC_S5J_CHIP_S5JT200_PWM_H */
